Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory;” and in U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory,” both patents are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states: an erased state and a programmed state (corresponding to data “1” and data “0”). Such a device is referred to as a binary device or a single-level cell (SLC) and the data is binary data.
A multi-state flash memory cell (storing multi-state data) is implemented by identifying multiple, distinct allowed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits. For example, some cells can store 2 bits, and others can store 3 bits. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the memory cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
In addition to the gains in capacity resulting from multi-state memory architectures, consumers have seen significant advantages as a result of a history of steadily scaling down the physical dimensions of memory cells. Smaller memory cells can be packed more densely on a given die area, allowing the user to access more memory capacity for the same price as an older memory technology. The shrinking of gate areas decreases the floating-gate-to-substrate capacitance as well as the control-gate-to-floating-gate capacitance. This decrease in capacitance in turn requires less charge for programming and erasing cells, thus consuming less power. The decrease in charge required for programming and erasing cells also means that, for similar charging and discharging currents, programming and erasing operations can be performed more quickly.
However, scaling the sizes of memory cells entails certain risks. As stated above, in order to achieve the advantage of higher memory capacity for a fixed die size, these smaller cells must be packed more closely together. Doing so, however, may result in a greater number of manufacturing errors, such as shorting between the word lines. Such errors usually corrupt any data stored on pages on the word lines being programmed and neighboring word lines. In some cases, these defects are not be realized during tests conducted by manufacturers prior to packaging and shipping. Rather, these defects only begin to corrupt data after program-erase cycles performed by the user.
For some memory systems, a technology known as Enhanced Post-Write Read (EPWR) exists in order to test for errors during programming. Data is first programmed into binary memory cells storing one bit per memory cell. Subsequently, data is re-programmed into multi-state memory cells storing three bits per memory cells. After programming the data into the multi-state memory cells that store three bits per memory cell, the data programmed is read and compared against that stored in the binary memory cells for verification of correct programming. If a difference is found, the block of multi-state memory cells is considered to be damaged and, therefore, retired from future use. The data is then re-programmed elsewhere. While this process has been useful, it does not satisfy all issues and can be expensive as the system needs to maintain blocks of memory cells to initially store the data before programming to multi-state memory cells. Additionally, this process results in a performance penalty and requires a larger amount of program/erase cycles.